1. Field of the Invention
The present invention relates to a convolutional interleaver/deinterleaver for correcting errors occurred in a data transmission of communication systems, and more particularly to a memory address generator in the convolutional interleaver/deinterleaver.
2. Description of Related Art
Generally, for correcting burst errors which may occur in the data transmission of the communication systems, an encoding part in the system has the interleaver and a decoding part has the deinterleaver. The interleaver and the deinterleaver delay a data for a predetermined length respectively and output the data after adjusting an order of the data using a memory device.
FIG. 1 is a conceptional diagram illustrating the interleaver/deinterleaver. Referring to FIG. 1, the interleaver includes "K" rows (K=12) and an unit cell 10 is a memory having "I" addresses in the direction of row. The first row of the interleaver includes a "0" unit cell, the second row a "1" unit cell and the last row "11" unit cells. That is, a K-th row includes "K-1" unit cells (in FIG. 1, K=12). For decoding interleaved data in the above-mentioned interleaver, the deinterleaver also includes "K" rows. The first row of the deinterleaver includes "K-1" unit cells, the second row "K-2" unit cells and a last row "zero" unit cell. Accordingly, the deinterleaved data has the same order as the data before interleaving because each row has the same delay time. And, in case of interleaving and deinterleaving, the data is transmitted with some delay among adjacent data during communication.
The above-mentioned interleaver/deinterleaver is implemented with memory. FIG. 2 is a block diagram illustrating a conventional memory address generator in the interleaver/deinterleaver. Referring to FIG. 2, the conventional memory address generator includes a plurality of counters generating a memory address for each row and a multiplexer for selecting one of the memory addresses outputted from the counters in response to a pointer. The counter in each row outputs and generates the memory address respectively. The multiplexer receives the memory address outputted from each counter and selects one of the memory addresses in response to the pointer. Namely, the selected memory address is the memory address of the convolutional interleaver/deinterleaver.
The above-mentioned memory address generator in the conventional interleaver/deinterleaver is in need of a multiplexer with multi-input and a large number of counters for generating the memory address of each row. Accordingly, the above-mentioned memory address generator has a large number of gates due to a large number of counters and a long critical path caused by the multiplexer.